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The pixel layout of the 2-inch (5.1-cm) display, which is based on the design for a small hand-held display, is shown in Fig. 1. First, the row electrodes are created by depositing and structuring a gold layer on a glass substrate. Next, an insulating layer of silicon nitride is applied. A second, patterned gold layer forms the column electrodes and the pixel pad. The pixel pad acts as an in-cell reflector, occupying 83% of the display area. On top of this stack, a polythienylenevinylene precursor film is spin-coated, converted into a semiconductor5 and patterned by photolithography. A spin-coated polyvinylphenol layer protects the active matrix.

Figure 1: Layout of one pixel (540 × 540 mm2) of an active-matrix display driven by transistors with a polymer semiconductor.
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The layout consists of the following layers: the row electrode (the gate; pink), insulator layer (blue), column electrode and pixel pad (the source and drain; green), semiconductor (red), protective layer (yellow), polymer-dispersed liquid-crystal layer (violet) and common electrode (grey), all sandwiched between two glass substrates (transparent). The length of the thin-film transistor (TFT) channel is 5 mm; the width is 400 mm.

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Spacers are sprayed on top of this active matrix. A second substrate, coated with indium tin oxide, is applied over the spacers and glued to the active matrix. Finally, the display is filled with polymer-dispersed liquid crystals6, thereby avoiding polarizers and an alignment layer. This technology yields a low-cost display with a high contrast and a wide viewing angle7, and even allows flexible displays to be produced8,9. A polymer-dispersed liquid-crystal pixel is switched between light-scattering and transparent states by applying a voltage between the electrical contacts.

The display is driven line-by-line. During one frame time, all rows are sequentially selected by applying a negative voltage that reduces the channel resistance of its thin-film transistors (TFTs). The column voltage is then transferred through the channel of the TFTs to the corresponding pixels. During the rest of the frame time, the channel resistance is high, thereby retaining the charge on the pixels while the other rows are addressed.

An image on the display is shown in Fig. 2. It contains 256 grey levels, as required for displaying natural scenes. The maximum contrast ratio is 8.6, which is comparable to that of black ink on paper. The columns are driven between −12 V and 12 V to switch the pixels. The rows, which are connected to the gate of the TFTs, are driven between −27 V and 27 V. The maximum on-current of the TFT is 0.8 μA; an average of 0.4 μA is sufficient to charge a pixel during the row-selection time. The field-effect mobility is 1.5 × 10−3 cm2 V−1 s−1. The off-current is below 20 pA, low enough to retain at least 99% of the pixel charge during the rest of the frame time. The on/off current ratio is 4 × 104, which matches the specifications for a display of this size. Because of the optimal pixel design, the display can be driven at refresh rates of up to 100 Hz.

Figure 2: An image on the multipixel display driven by 4,096 thin-film transistors, with a solution-processed polythienylenevinylene semiconductor.
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The image contains 256 grey levels; the display is refreshed at 50 Hz.

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Well defined grey levels require sufficient control of the 'spread' on the TFT parameters such as mobility, leakage current and threshold voltage. Measurements show a standard deviation in the contrast of a typical line in the display of 0.11 for white pixels and 0.14 for pixels switched to mid-grey. This small difference indicates that the spread on TFT parameters is only a minor factor in the uniformity of this display. We intend to optimize our solution-based technology to obtain the same uniformity over an even larger area, paving the way for a low-cost production process for large sheets of electronic paper.