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Vertically stacked multi-heterostructures of layered materials for logic transistors and complementary inverters

Abstract

Graphene has attracted considerable interest for future electronics, but the absence of a bandgap limits its direct applicability in transistors and logic devices. Recently, other layered materials such as molybdenum disulphide (MoS2) have been investigated to address this challenge. Here, we report the vertical integration of multi-heterostructures of layered materials for the fabrication of a new generation of vertical field-effect transistors (VFETs) with a room temperature on–off ratio > 103 and a high current density of up to 5,000 A cm−2. An n-channel VFET is created by sandwiching few-layer MoS2 as the semiconducting channel between a monolayer graphene sheet and a metal thin film. This approach offers a general strategy for the vertical integration of p- and n-channel transistors for high-performance logic applications. As an example, we demonstrate a complementary inverter with a larger-than-unity voltage gain by vertically stacking graphene, Bi2Sr2Co2O8 (p-channel), graphene, MoS2 (n-channel) and a metal thin film in sequence. The ability to simultaneously achieve a high on–off ratio, a high current density and a logic function in such vertically stacked multi-heterostructures can open up possibilities for three-dimensional integration in future electronics.

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Figure 1: Schematic illustration of the vertically stacked graphene–MoS2–metal FETs.
Figure 2: Fabrication and structural characterization of the vertical transistor.
Figure 3: Room-temperature electrical properties of the vertical and planar transistors.
Figure 4: Schematic illustration of the band diagrams of the vertical transistors and the electrical characteristics.
Figure 5: Vertically stacked multi-heterostructures of layered materials for complementary inverters.

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Acknowledgements

We acknowledge the Nanoelectronics Research Facility and the Electron Imaging Center for Nanomachines (EICN) at UCLA for technical support of device fabrication and TEM characterization. We are grateful to I. Terasaki of Nagoya University for providing the BSCO samples. W.J.Y. acknowledges partial support by the National Research Foundation of Korea Grant funded by the Korean Government (NRF-2011-351-C00034). Z.L. is a visiting student from the Department of Physics, Peking University, sponsored by the UCLA cross-disciplinary scholars in science and technology (CSST) programme. H.Z. is grateful to the Camille and Henry Dreyfus Foundation for financial support through the Camille and Henry Dreyfus Postdoctoral Program in Environmental Chemistry (X.D.). X.D. acknowledges partial support by NSF CAREER award 0956171 (device fabrication and characterization) and ONR Young Investigator Award N00014-12-1-0745 (simulation). Y.H. acknowledges the NIH Director’s New Innovator Award Program 1DP2OD007279 (TEM characterization and preparation of BSCO sample).

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X.D conceived the research. X.D. and W.J.Y. designed the experiment. W.J.Y. performed most of the experiments including device fabrication, characterization and data analysis. Z.L. performed the simulations. H.Z. synthesized the graphene samples. Y.C. performed the TEM studies. Y.W. contributed to the preparation of BSCO flakes. Y.H. and X.D. supervised the research. X.D. and W.J.Y. co-wrote the paper. All authors discussed the results and commented on the manuscript.

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Correspondence to Xiangfeng Duan.

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The authors declare no competing financial interests.

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Yu, W., Li, Z., Zhou, H. et al. Vertically stacked multi-heterostructures of layered materials for logic transistors and complementary inverters. Nature Mater 12, 246–252 (2013). https://doi.org/10.1038/nmat3518

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