Abstract
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
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References
Sakurai, T. Perspectives of low power VLSI's. IEICE Trans. Electron E87-C, 429–436 (IEICE, 2004).
Bernstein, K., Cavin, R. K., Porod, W., Seabaugh A. C. & Welser, J. Device and architectures outlook for beyond CMOS switches. Proc. IEEE 98, 2169–2184 (2010).
Seabaugh, A. C. & Zhang, Q. Low voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98, 2095–2110 (2010).
Sze, S. M. Physics of Semiconductor Devices, 1st edn (John Wiley, 1969).
Lundstrom, M. S. The MOSFET revisited: device physics and modeling at the nanoscale. Proc. IEEE Int. SOI Conf. 1–3 (IEEE, 2006).
Kim, D. et al. Heterojunction tunneling transistor (HETT)-based extremely low power applications. Proc. Int. Symp. Low Power Electron. Design 219–224 (IEEE/ACM, 2009).
Bhuwalka, K., Schultze, J. & Eisele, I. A simulation approach to optimize the electrical parameters of a vertical tunnel FET. IEEE Trans. Electron Devices 52, 1541–1547 (2005).
Boucart, K. & Ionescu, A. M. Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans. Electron Devices 54, 1725–1733 (2007).
Kam, H., King-Liu, T.-J., Alon, E. & Horowitz, M. Circuit-level requirements for MOSFET-replacement devices. Tech. Digest IEEE Int. Electron Devices Meet. 1 (IEEE, 2008).
Hanson, S., Seok, M., Sylvester, D. & Blaauw, D. Nanometer device scaling in subthrehold logic and SRAM. IEEE Trans. Electron Devices 55, 175–185 (2008).
Chang, L. et al. Practical strategies for power-efficient computing technologies. Proc. IEEE 98, 215–236 (2010).
Nose, K. & Sakurai, T. Optimization of V DD and V TH for low-power and high-speed applications. Proc. Asia S. Pacif. Design Automat. Conf. 469–474 (ACM, 2000).
Gopalakrishnan, K., Griffin, P. B. & Plummer, J. D. I-MOS: a novel semiconductor device with subthreshold slope lower than kT/q. Tech. Digest IEEE Int. Electron Devices Meet. 289–292 (IEEE, 2002).
Zener, C. A theory of electrical breakdown of solid dielectrics. Proc. R. Soc. Lond. A 145, 523–529 (1934).
Salahuddin, S. & Datta, S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett. 8, 405–410 (2008).
Salvatore, G. A., Bouvet, D. & Ionescu, A. M. Demonstration of subthreshold swing smaller than 60mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 gate stack. Tech. Digest IEEE Int. Electron Devices Meet. 1–4 (IEEE, 2008).
Rusu, A., Salvatore, G. A., Jimenez, D. & Ionescu, A. M. Metal-ferroelectric-meta-oxide-semiconductor field effect transistor with sub-60mV/decade subthreshold swing and internal voltage amplification. IEEE Int. Electron Devices Meet. 16.3.1–16.3.4 (IEEE, 2010).
Abele, N. et al. Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor. Tech. Digest IEEE Int. Electron Devices Meet. 479–481 (IEEE, 2005).
Chen, F. et al. Integrated circuit design with NEM relays. IEEE/ACM Int. Conf. Computer-Aided Design 750–757 (IEEE, 2008).
Pott, V., Hei Kam, N. R., Jaeseok, J., Alon, E. & Tsu-Jae, K. L. Mechanical computing redux: relays for integrated circuit applications. Proc. IEEE 98, 2076–2094 (2010).
Quinn, J., Kawamoto, G. & McCombe, B. Subband spectroscopy by surface channel tunneling. Surf. Sci. 73, 190–196 (1978).
Banerjee, S., Richardson W., Coleman J. & Chatterjee, A. A new three-terminal tunnel device. IEEE Electron Device Lett. 8, 347–349 (1987).
Takeda, E., Matsuoka, H., Igura, Y. & Asai, S. A band to band tunneling MOS device B2T-MOSFET. Tech. Digest IEEE Int. Electron Devices Meet. 402–405 (IEEE, 1988).
Baba, T. Proposal for surface tunnel transistors. Jpn. J. Appl. Phys. 31, L455–L457 (1992).
Reddick, W. & Amaratunga, G. Silicon surface tunnel transistor. Appl. Phys. Lett. 67, 494–496 (1995).
Koga, J. & Toriumi, A. Negative differential conductance in three-terminal silicon tunneling device. Appl. Phys. Lett. 69, 1435–1437 (1996).
Hansch, W., Fink, C., Schulze, J. & Eisele, I. A vertical MOS-gated Esaki tunneling transistor in silicon. Thin Solid Films 369, 387–389 (2000).
Aydin, C. et al. Lateral interband tunneling transistor in silicon-on-insulator. Appl. Phys. Lett. 84, 1780–1782 (2004).
Appenzeller, J., Lin, Y.-M., Knoch J. & Avouris, P. Band-to-band tunneling in carbon nanotube field-effect transistors. Phys. Rev. Lett. 93, 196805 (2004).
Krishnamohan, T., Kim, D., Raghunathan, S. & Saraswat, K. Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and <60 mV/dec subthreshold slope. Tech. Digest IEEE Int. Electron Devices Meet. 947–949 (IEEE, 2008).
Mayer, F. et al. Impact of SOI, Si1–xGexOI and GeOI substrates on CMOS compatible tunnel FET performance. Tech. Digest IEEE Int. Electron Devices Meet. 163–166 (IEEE, 2008).
Hu, C. et al. Prospect of tunneling green transistor for 0.1 V CMOS. IEEE Int. Electron Devices Meet. 16.1.1–16.1.4 (IEEE, 2010).
Moselund, K. E. et al. Comparison of VLS grown Si NW tunnel FETs with different gate stacks. Proc. Eur. Solid State Device Res. Conf. 448–451 (IEEE, 2009).
Wang, P. F. et al. Complementary tunneling transistor for low power application. Solid-State Electron. 48, 2281–2286 (2004).
Knoch, J. & Appenzeller, J. A novel concept for field-effect transistors – the tunneling carbon nanotube FET. Digest Device Res. Conf. 153–156 (IEEE, 2006).
Knoch, J., Mantl, S. & Appenzeller, J. Impact of the dimensionality on the performance of tunneling FETs: bulk versus one-dimensional devices. Solid-State Electron. 51, 572–578 (2007).
Zhang, Q., Zhao, W. & Seabaugh, A. Low-subthreshold-swing tunnel transistors. IEEE Electron Device Lett. 27, 297–300 (2006).
Luisier, M. & Klimeck, G. Simulation of nanowire tunneling transistors: from the Wentzel–Kramers–Brillouin approximation to full-band phonon-assisted tunneling. J. Appl. Phys. 107, 084507 (2010).
Appenzeller, J., Knoch, J., Björk, M. T., Riel, H. & Riess, W. Toward nanowire electronics. IEEE Trans. Electron Devices 55, 2827–2845 (2008).
Ionescu, A. M., Boucart, K., Moselund, K. E. & Pott, V. Small Swing Switches (Cambridge Univ. Press, in the press).
Leonelli, D. et al. Optimization of tunnel FETs: impact of gate oxide thickness, implantation and annealing conditions. Proc. Eur. Solid State Device Res. Conf. 170–173 (IEEE, 2010).
Boucart, K. & Ionescu, A. M. Length scaling of the double gate tunnel FET with a high-κ gate dielectric. Solid State Electron. 51, 1500–1507 (2007).
Sandow, C., Knoch, J., Urban, C., Zhao, Q.-T. & Mantl, S. Impact of electrostatics and doping concentration on the performance of silicon tunnel field-effect transistors. Solid State Electron. 53, 1126–1129 (2009).
Bhuwalka, K., Schulze, J. & Eisele, I. Performance enhancement of vertical tunnel field-effect transistor with SiGe in the dp+ layer. Jpn. J. Appl. Phys. 43, 4073–4078 (2004).
Verhulst, A. et al. Complementary silicon-based heterostructure tunnel-FETs with high tunnel rates. IEEE Electron Device Lett. 29, 1398–1401 (2008).
Knoch, J. Optimizing tunnel FET performance–impact of device structure, transistor dimensions and choice of material. Int. Symp. VLSI-TSA 45–46 (IEEE, 2009).
Knoch, J. & Appenzeller, J. Modeling of high-performance p-type III–V heterojunction tunnel FETs. IEEE Electron Device Lett. 31, 305–307 (2010).
Koswatta, S. O., Koester, S. J. & Haensch, W. On the possibility of obtaining MOSFET-like performance and sub-60-mV/dec swing in 1-D broken-gap tunnel transistors. IEEE Trans. Electron Devices 57, 3222–3223 (2010).
Hu, C. Green transistor as a solution to the IC power crisis. Proc. 9th Int. Conf. Solid-State Integrated-Circuit Technol. 16–20 (IEEE, 2008).
Hu, C. et al. Prospect of tunneling green transistor for 0.1 V CMOS. IEEE Int. Electron Devices Meet. 16.1.1–16.1.4 (IEEE, 2010).
Asra, R. et al. A tunnel FET for V DD scaling below 0.6V with a CMOS-comparable performance. IEEE Trans. Electron Devices 58, 1855–1863 (2011).
De Michielis, L., Lattanzio, L., Palestri, P., Selmi L. & Ionescu, A. M. Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier. IEEE Device Res. Conf. (IEEE, in the press).
Nayfeh, O. M. et al. Design of tunneling field-effect transistors using strained-silicon/strained-germanium type-II staggered heterojunctions. IEEE Electron Device Lett. 29, 1074–1077 (2008).
Boucart, K., Ionescu, A. M. & Riess, W. Asymmetrically strained all-silicon tunnel FETs featuring 1V operation. Proc. Eur. Solid State Device Res. Conf. 452–456 (IEEE, 2009).
Boucart, K., Riess, W. & Ionescu, A. M. Lateral strain profile as key technology booster for all-silicon tunnel FETs. IEEE Electron Device Lett. 30, 656–658 (2009).
Boucart, K. Simulation of a Double Gate Silicon Tunnel FET with a High-κ Dielectric. PhD thesis, Ecole Polytechnoique Fédérale de Lausanne (2009).
Le Royer, C. & Mayer, F. Exhaustive experimental study of tunnel field effect transistors (TFETs): from materials to architecture. Proc. 10th Int. Conf. Ultimate Integration Silicon 53–56 (IEEE, 2009).
Loh, W.-Y. et al. Sub-60nm Si tunnel field effect transistors with I on > 100 μA/ μm. Proc. Eur. Solid State Device Res. Conf. 162–165 (IEEE, 2010).
Mookerjea, S. et al. Experimental demonstration of 100 nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFET) for ultra low-power logic and SRMA applications. IEEE Int. Electron Devices Meet. 137.1–137.4 (IEEE, 2009).
Zhao, H. et al. InGaAs tunneling field-effect transistors with atomic-layer-deposited gate oxides. IEEE Trans. Electron Devices 58, 2990–2995 (2011).
Mookerjea, S., Mohata, D., Mayer, T., Narayanan V. & Datta, S. Temperature-dependent characteristics of a vertical tunnel FET. IEEE Electron Device Lett. 31, 564–566 (2010).
Wang, L., Yu, E., Taur Y. & Asbeck, P. Design of tunneling field-effect transistors based on staggered heterojunctions for ultralow-power applications. IEEE Electron Device Lett. 31, 431–433 (2010).
Mohata, D. et al. Experimental staggered-source and N+ pocket-doped channel III–V tunnel field-effect transistors and their scalabilities. Appl. Phys. Express 4, 024105 (2011).
Zhou, G. et al. Self-aligned InAs/Al0.45Ga0.55Sb vertical tunnel FETs. IEEE Device Res. Conf. 205–206 (IEEE, 2011).
Tomioka, K., Motohisa, J., Hara S. & Fukui, T. Control of InAs nanowire growth directions on Si. Nano Lett. 8, 3475–3480 (2008).
Björk, M. T. et al. Si–InAs heterojunction Esaki tunnel diodes with high current densities. Appl. Phys. Lett. 97, 163501 (2010).
Bessire, C. D. et al. Trap-assisted tunneling in Si–InAs nanowire heterojunction tunnel diodes. Nano Lett. 11, 4195–4199 (2011).
Lu, Y. et al. Geometry dependent tunnel FET performance — dilemma of electrostatics vs. quantum confinement. IEEE Device Res. Conf. 17–18 (IEEE, 2010).
Schmid, H. et al. Fabrication of vertical InAs–Si heterojunction tunnel field effect transistors. IEEE Proc. Device Res. Conf. 181–182 (2011).
Poli, S. et al. Computational study of the ultimate scaling limits of CNT tunneling devices. IEEE Trans. Electron Devices 55, 313–321 (2008).
Koswatta, S. O., Lundstrom, M. S. & Nikonov, D. E. Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon-assisted tunneling. Nano Lett. 7, 1160–1164 (2007).
Appenzeller, J., Lin, Y.-M., Knoch, J., Chen, Z. & Avouris, P. Comparing carbon nanotube transistors — the ideal choice: a novel tunneling device design. IEEE Trans. Electron Devices 52, 2568–2576 (2005).
Zhang, Y. et al. Giant phonon-induced conductance in scanning tunneling spectroscopy of gate-tunable graphene. Nature Phys. 4, 627–630 (2008).
Luisier, M. & Klimeck, G. Performance limitations of graphene nano ribbon tunneling FETS due to line edge roughness. IEEE Device Res. Conf. 201–202 (IEEE, 2009).
Fiori, G. & Iannaccone, G. Ultralow-voltage bilayer graphene tunnel FET. IEEE Electron Device Lett. 30, 1096–1098 (2009).
ITRS International Technology Working Groups. International Technology Roadmap for Semiconductors 〈http://www.itrs.net〉 (2010).
Mookerjea, S., Krishnan, R., Datta, S. & Narayanan, V. On enhanced Miller capacitance effect in interband tunnel transistors. IEEE Electron Device Lett. 30, 1102–1104 (2009).
Koswatta, S., Lundstrom, M. & Nikonov, D. Performance comparison between p-i-n tunneling transistors and conventional MOSFETs. IEEE Trans. Electron Devices 56, 456–465 (2009).
Solomon, P. M., Frank, D. J. & Koswatta, S. O. Compact model and performance estimation for tunneling nanowire FET. IEEE Device Res. Conf. 197–198 (IEEE, 2011).
Born, M. et al. Tunnel FET: a CMOS device for high temperature applications. Proc. 25th Int. Conf. Microelectron. 124–127 (IEEE, 2006).
Fulde, M. et al. Fabrication, optimization, and application of complementary multiple-gate tunneling FETs. Proc. INEC 579–584 (IEEE, 2008).
Kane, E. O. Zener tunneling in semiconductors. J. Phys. Chem. Solids 12, 181–188 (1959).
Mookerjea, S., Mohata, D., Mayer, T., Narayanan, V. & Datta, S. Temperature-dependent I–V characteristics of a vertical In0.53Ga0.47As tunnel FET. IEEE Electron Device Lett. 31, 564–566 (2010).
Moselund, K. E. et al. Silicon nanowire tunnel FETs: low-temperature operation and influence of high-k gate dielectric. IEEE Trans. Electron Devices 58, 2911–2916 (2011).
Singh, J. et al. A novel Si-tunnel FET based SRAM design for ultra low-power 0.3 V V DD applications. Proc. Asia S. Pacif. Design Automat. Conf. 181–186 (ACM, 2010).
Saripalli, V., Mohata, D. K., Mookerjea, S., Datta, S. & Narayanan, V. Low power loadless 4T SRAM cell based on degenerately doped source (DDS) In0.53Ga0.47As tunnel FETs. IEEE Device Res. Conf. 101–102 (IEEE, 2010).
Acknowledgements
Some of this work was supported by the European Commission under the FP7 projects Guardian Angels for a Smarter Life and STEEPER. K. Boucart, L. De Michielis, C. Le Royer, K. Moselund, M. Björk, H. Schmid, W. Riess and P. Solomon are particularly acknowledged for useful discussions and supporting materials.
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Ionescu, A., Riel, H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011). https://doi.org/10.1038/nature10679
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