Introduction

The potential of atomically thin two-dimensional layered materials in meeting the performance requirements of international technology roadmap for semiconductors1 has spun off intense research efforts on graphene2,3, transition metal dichalcogenides (TMD)4 and most recently black phosphorus (BP) crystal5. In particular, BP is known to be a promising channel material for future nanoelectronics applications owing to its superior carrier transport and direct bandgap properties for all layer thicknesses. This ranges from ~0.3 eV in the bulk form6,7 and increases to ~2 eV when the BP thickness is reduced to monolayer form8. Excellent electron and hole mobilities reaching ~15,000 cm2V−1s−1 and ~50,000 cm2V−1s−1, respectively, have also been reported in bulk BP single crystal7. Although a handful of BP transistors have been previously demonstrated9,10,11,12,13,14,15,16,17, the device performance is still far from satisfactory. Furthermore, to be CMOS compatible, the integration of a high-temperature thermal anneal is typically required to improve device performance. Some initial studies on the role of temperature on BP film structure and device performance have been reported18,19,20,21,22. With increasing anneal temperatures, Liu et al.19 showed the decomposition of BP film at 400 °C and a temperature induced increase in lattice parameters as confirmed by in situ scanning/transmission electron microscopy measurements in the vacuum state. For practical applications, surface passivation of the BP channel is necessary to address photo-oxidation issue23. When BP is passivated with hexagonal boron nitride (h-BN), an insulating 2D material, the device shows a significantly higher temperature tolerance up to 500 °C18. The high temperature anneal can help to suppress the charge trap states, leading to low hysteresis, improved mobility and high on-off ratios (>105). Although h-BN is a possible candidate for device integration, the relatively low dielectric constant (<4)24 severely limits its potential for highly scaled transistors. Thus, there is a demand for suitable high-k gate dielectrics to improve the device performance. One possible high-k dielectric candidate is hafnium-dioxide (HfO2) which has a dielectric constant of ~2525, which is six times higher than the conventional SiO2 dielectric. Although some preliminary BP transistors have been realized on HfO2 or Al2O3 gate dielectric, poor subthreshold swing performance of the order of 0.3~1.1 V/dec and carrier mobility below ~310 cm2V−1s−1 were reported. Moreover, there are limited reports on the application of thermal treatment to improve the BP/high-k interface quality for enabling further performance enhancement.

In this work, we report the realization of BP transistors with a near ideal subthreshold swing (~66 mV/dec) and enhanced hole mobility (~536 cm2V−1s−1) through the use of an ultra-thin hafnium-dioxide (HfO2) gate dielectric and interface engineering. We further investigate the influence of thermal treatment on the structural and electrical properties of the BP transistors. Detailed material studies are performed using X-ray photoelectron spectroscopy, Raman spectroscopy and energy-dispersive X-ray spectroscopy to analyze the structural integrity and interface properties between the BP and HfO2 gate dielectric. Comprehensive electrical performance metrics including subthreshold swing, hole mobility, transfer characteristics and channel resistance are systematically analyzed.

Results and Discussion

Figure 1 shows the low temperature fabrication flow used to realize the black phosphorus (BP) transistor with an ultra-thin high-k gate dielectric. The devices feature a back-gate configuration with a minimum gate length of ~3 μm. A CMOS-compatible metal such as nickel (Ni) was used to form the metal electrodes26. The as-fabricated transistor was passivated with a 30 nm silicon-dioxide (SiO2) layer deposited by e-beam evaporator at room temperature to protect the device from photo-oxidation in the ambient condition. A detailed description of the process is provided in the experimental method section. The devices realized in this work demonstrate a clear p-type behavior as depicted in Fig. 2, in which the room temperature transfer curves (IDS - VG) are plotted at the same drain voltage (VDS) of −100 mV. In the as-fabricated state, the BP transistor shows a significantly improved subthreshold swing (SS) of ~76 mV/dec as compared to other BP transistors based on traditional SiO2 gate dielectric (SS > 1 V/dec)9,10,11,12,13,14,15,16,17 or Al2O3 gate dielectric (SS ~ 350–850 mV/dec)15,27, as benchmarked in Fig. 3. The improved SS performance implies the effectiveness of ultra-thin high-k gate dielectric in providing excellent gate control over the source-to-drain current, which enables BP transistor to achieve better electrostatics control. When subjected to an additional interface anneal for one minute under nitrogen (N2) ambient, the SS performance was shown to improve further and reaching a near ideal value of 66 mV/dec at room temperature (T = 300 K). Such a significant improvement is resulted from a better BP/HfO2 interface due to the passivation of phosphorus dangling bonds by hafnium (Hf) adatoms as promoted by the thermal treatment. This can be evidenced from the strong P-Hf binding energy at ~135.6 eV over the P-P binding energy at ~131.1 eV, as confirmed by the P 2p core level obtained from X-ray photoelectron spectroscopy (XPS) measurement in Fig. 4. The binding energies of all spectra are referenced to C1s which is set to 285 eV. The appearance of P-P peak or the single spin-orbit split doublet at a binding energy of ~131 eV indicates the intrinsic crystallinity of the exfoliated BP on HfO2 gate dielectric, which is consistent with previous XPS measurements on BP bulk crystals28,29. To understand the interaction between Hf and P, first-principles calculations were performed within the density-functional theory (DFT) framework. The results show that Hf adatom prefers the adsorption position above the center of P6 hexagonal ring or H-site of the phosphorene layer (see inset of Fig. 4), which is consistent with other transition metals reported in previous studies30. When this occurs, Hf adatom forms strong covalent bond with phosphorene with a binding energy of −4.17 eV. The stronger P-Hf binding has been found to be consistent with a shorter P-Hf bond and larger deformation of phosphorene layer.

Figure 1
figure 1

The fabrication flow for the black phosphorus transistor based on low temperature CMOS-compatible processes.

(a) Using a degenerately doped Si substrate, an ultra-thin hafnium-dioxide gate dielectric of ~3.4 nm is deposited using atomic layer deposition (ALD) technique at a temperature of 250 °C. (b) BP nanosheet with a ~15 nm thickness is micromechanically exfoliated onto the high-k gate dielectric. (c) Metal electrodes utilizing nickel with a thickness of 120 nm are formed by a combination of electron beam lithography and electron-beam evaporation followed by the lift-off process. (d) An additional surface passivation by a 30 nm thick SiO2 layer is deposited to protect the as-fabricated devices from photo-oxidation in ambient conditions.

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Figure 2
figure 2

A comparison of the transfer characteristics of the black phosphorus transistors with and without interface annealing.

With an excessively high thermal budget, the subthreshold swing of the BP transistor can be significantly degraded, which is attributed to the detrimental change of the BP film crystallinity. When subjected to a 100 °C thermal anneal, an off-state current of ~8.09 × 10−7 A was measured in the BP transistor. However, an improved hysteresis performance was estimated in devices which were annealed at 100 °C as compared to the un-annealed devices. This further confirms the achievement of lower Dit due to an optimum thermal annealing.

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Figure 3
figure 3

Figure-of-merit showing the relationship between gate dielectric thickness and the subthreshold swing (SS) performance of black phosphorus transistors.

A significant SS improvement is observed by downscaling the thickness to ~3.4 nm coupled with an interface anneal process, showing a near ideal value of ~66 mV/dec. This is by far the lowest SS reported, which indicates an enhanced electrostatics control in the BP transistors.

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Figure 4
figure 4

The P 2p core level of X-ray photoelectron spectra (XPS) for the black phosphorus nanosheet formed on HfO2 gate dielectric.

A thermal treatment at 100 °C under nitrogen ambient improves the binding energy of P-Hf, which allows the achievement of better interface quality between BP and HfO2. The inset shows the formation of covalent bonds between P and Hf adatoms with a strong binding energy of −4.17 eV, as confirmed by the first-principles calculation within the density-functional theory (DFT) framework.

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To estimate the effective interface state density Dit, the subthreshold swing equation can be employed31, where k is the Boltzmann constant, T is the temperature in Kelvin, q is the electronic charge, CS is the depletion capacitance of BP, Cit is the BP/HfO2 interface state capacitance and COX is the unit gate capacitance. When the applied gate voltage approaches the threshold voltage, the thin pristine BP channel is expected to be fully depleted where the depletion capacitance (Cs) is small as compared to the interface state capacitance (Cit). The effective interface state density Dit at BP/HfO2 interface can then be estimated using the expression . To give better Dit estimation, we have included the contribution of Cs in the calculation where the dielectric constant of BP is taken as 6.1εo32 while the depletion width is equal to the thin BP thickness of 15 nm. Based on the extracted SS of 66 mV/dec (annealed) and ~76 mV/dec (un-annealed), the effective interface state density Dit at the BP/HfO2 interface is estimated to be ~6.08 × 1011 cm−2eV−1 and ~5.07 × 1012 cm−2eV−1, respectively. The substantial reduction in Dit by ~88% further confirms the effectiveness of Hf adatoms in passivating the P dangling bonds at the BP/HfO2 interface, which accounts for the SS improvement.

By extracting the slope in the linear region of the transfer curve, the mobility can be evaluated using the expression where L is the channel length, W is the channel width, COX is the capacitance between the channel and the back-gate per unit area and VDS is the voltage between the source and drain electrodes5. The extracted field-effect mobility (μFE) at room temperature is plotted in Fig. 5 and benchmarked against other BP transistors based on traditional SiO2 or Al2O3 gate dielectrics. Even in the absence of thermal treatment, the as-fabricated BP transistor achieves a relatively high μFE of 413 cm2V−1s−1. Note worthily, the μFE was shown to significantly improve by ~30% to 536 cm2V−1s−1 when the device was treated at an elevated temperature of 100 °C in nitrogen (N2) ambient. This is believed to be a record-high hole mobility among other reported data based on HfO2 or Al2O3 high-k gate dielectrics at room temperature (T = 300 K). Such an improvement was believed to be attributed to a better BP/HfO2 interface as a result of phosphorus dangling bonds passivation as discussed in the preceding section. However, a further increase in the thermal budget has been found to degrade the carrier mobility. Noticeably, the μFE was drastically reduced to 120 cm2V−1s−1 after going through a 200 °C anneal. In order to understand the underlying mechanisms, the BP film structure properties were analyzed using confocal Raman spectroscopy. Figure 6(a) plots the Raman spectra of the BP flake formed on 3.4 nm HfO2 gate dielectric with a 30 nm SiO2 passivation layer. When annealed at an elevated temperature, a shift in the Raman phonon peak positions corresponding to A1g, B2g and A2g was clearly evident which is indicative of the film structure modification. A deconvolution of the characteristics out-of-plane mode (A1g) and in-plane modes (B2g and A2g) in Fig. 6(a–c), respectively, further confirms the Raman peak position shifts. Interestingly, the samples in this work exhibited a general blue shift with increasing temperatures up to 200 °C. A significant blue shift of 0.53 cm−1, 1.0 cm−1 and 1.1 cm−1 for the A1g, B2g and A2g vibrational modes, respectively, was observed as compared to the un-annealed case. In contrast, when a conventional SiO2 dielectric was utilized, both Dattatray21 and Zhang et al.22 experimentally showed a rather linear red shift in all three vibrational modes with increasing temperatures from 77 K up to 673 K.

Figure 5
figure 5

Figure-of-merit showing the relationship between gate dielectric thickness and room temperature hole mobility of black phosphorus transistors.

A better BP/HfO2 interface quality due to the passivation of phosphorus dangling bonds by hafnium (Hf) adatoms has been shown to result in an enhanced hole mobility over the un-annealed device. A mean mobility of ~413 cm2V−1S−1 and ~536 cm2V−1S−1 were achieved for devices with no anneal and 100 °C anneal, respectively. A further increase of thermal budget beyond 200 °C could significantly degrade the carrier transport due to crystal lattice distortion and impurity scattering effect, leading to a low mean mobility of ~120 cm2V−1S−1.

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Figure 6
figure 6

(a) Raman spectra of the exfoliated BP nanosheets showed the three characteristic vibrational modes after underwent different thermal anneal for a duration of one minute in nitrogen (N2) ambient. The deconvoluted Raman peaks corresponding to the out-of-plane phonon mode A1g and in-plane phonon modes B2g and A2g, are plotted in (b–d), respectively. A clear Raman peak shift is evident with increasing interface anneal temperature, which indicates film structure modification.

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To understand this shift further, the first-principles linear response method from Fei et al.33 can be employed. In particular, the effect of zigzag and armchair strain on the puckered honeycomb structure of the black phosphorus will lead to a shift in the Raman peak positions of the characteristics phonon modes depending on the nature of the strain (tensile or compressive). Comparing our results to the first-principles studies, it appears to indicate the presence of compressive strain in both the zigzag and armchair directions for an anneal temperature up to 200 °C, which is clearly evident from the blue shift of the A1g, B2g and A2g modes. This could be attributed to the out-diffusion of hafnium (Hf) adatoms from the underlying high-k gate dielectric which compresses the BP channel. According to Clementi et al.34, the atomic radii of the hafnium (Hf) atoms is 2.08 Å, which is almost two times that of the silicon atoms. In comparison, the atomic radii of the oxygen atoms is 0.48 Å, significantly lower than the hafnium (Hf), silicon (Si) and even the phosphorus (P) atoms (0.98 Å). Hence, in the event of out-diffusion into the BP film, the atom with the largest atomic radii (Hf in our case) is likely to dominate the compressive strain observed. Thus, the incorporation of Hf with a larger atomic radii will be expected to result in crystal lattice distortion in the zigzag direction which will lead to elastic strain effect. However, with a further increase in strain beyond its critical limit, plastic relaxation will eventually occur which causes the crystal lattice to be distorted. When this occurs, the crystalline quality of black phosphorus would be expected to degrade, as evident by the broadening of the full-width at half maximum (FWHM) for both the B2g and A2g vibrational modes35.

To confirm the out-diffusion of adatoms, energy-dispersive X-ray spectroscopy (EDX) measurements were performed on the annealed samples to analyze the BP/HfO2 interface, as plotted in Fig. 7. It is worthy to note that the degree of hafnium (Hf) and oxygen (O) out-diffusion from the underlying HfO2 gate dielectric depends strongly on the thermal budget38,39. When annealed at a temperature of 100 °C, the out-diffused Hf adatoms were predominantly found at the BP/HfO2 interface which could promote the passivation of P dangling bonds [Fig. 7(a)]. However, when the thermal budget was further increased to 200 °C, a substantial amount of Hf adatoms were found to diffuse deeper into the BP channel [Fig. 7(b)]. Given the puckered honeycomb structure of BP, these out-diffused adatoms are likely to preferentially occupy the H-site in the zigzag (B2g and A2g) direction which has been theoretically predicted for most transition metals in phosphorene30. This is believed to be responsible for the compressive strain observed in the BP nanosheet after a high temperature anneal. Moreover, these out-diffused adatoms could also act as impurities scattering centers which would detrimentally increase the channel resistance and degrade the carrier transport properties.

Figure 7
figure 7

The energy-dispersive X-ray (EDX) spectroscopy measurement confirms the out-diffusion of Hf adatoms from the underlying HfO2 gate dielectric into BP film when subjected to thermal treatment.

(a) With a lower thermal budget of 100 °C, the out-diffused Hf adatoms were predominantly found at the BP/HfO2 interface which promotes the passivation of P dangling bonds. (b) However with a further increase of thermal budget to 200 °C, a substantial out-diffusion of Hf adatoms was detected in the BP channel which is responsible for the carrier transport degradation in BP transistors.

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To gain a further insight into the impact of impurities scattering centers on channel resistance, the transfer length method (TLM) was employed in which the total normalized resistance (RtotW) was plotted as a function of channel length (L) as shown in Fig. 8. Using this approach, the contact resistance can be determined by the y-intercept of the width normalized total resistance. The channel resistance can also be determined by subtracting the contact resistance from the total resistance, which is summarized in the inset of Fig. 8 as a function of thermal budget. When subjected to a thermal treatment at 100 °C, the BP structural integrity was found to remain intact, as evident by the comparable channel and contact resistances over the un-annealed case. On the contrary, a high degree of crystal lattice distortion was present in the BP film after a 200 °C thermal treatment, as supported by the Raman phonon shifts in Fig. 6. This is found to be detrimental for device performance, which is evident from the higher channel resistance by 5× as compared to the un-annealed devices. Apart from channel resistance degradation, the contact resistance has also been found to increase after a 200 °C anneal in which the 2Rc approaches ~145.3 Ω-mm. This is substantially higher than the contact resistance measured in devices which underwent 100 °C or no anneal, where the 2Rc was merely ~20.5 Ω-mm. Such a degradation is likely to be attributed to the crystal lattice distortion which causes a poorer interface quality between the metal and the BP layer. The adsorption of Hf adatoms in BP could also additionally cause an increased impurities scattering effect37 which would compromise the carrier transport in BP transistors. This is consistent with the lower hole mobility of 120 cm2V−1s−1 and poorer subthreshold swing SS of ~780 mV/dec discussed earlier. Hence, an optimization of the thermal treatment process is critically important to effectively engineer the interface quality between BP and HfO2 high-k gate dielectric for enabling further performance boost.

Figure 8
figure 8

Using the transfer length method (TLM), the total normalized resistance (RtotW) was plotted as a function of channel length (L).

Comparable contact and channel resistance were achieved for a thermal anneal of 100 °C as compared to the un-annealed case. However, an elevated thermal treatment at 200 °C could result in a detrimental change to the BP film structure, which leads to both channel and contact resistance degradation.

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Conclusions

In conclusion, we have experimentally demonstrated black phosphorus transistor with enhanced carrier transport through interface engineering between BP and high-k gate dielectric. A high room temperature hole mobility of ~536 cm2V−1s−1 and a near ideal subthreshold swing of ~66 mV/dec were simultaneously achieved. Such a performance enhancement is attributed to the better interface quality between BP and HfO2 as a result of phosphorus dangling bonds passivation by hafnium adatoms, which leads to a significant reduction in interface state density. Excessively high treatment temperature could promote the out-diffusion of hafnium adatoms into the BP channel, which distorts its crystal lattice and results in carrier transport degradation. Our study contributes to the development of BP-based transistor with enhanced performance through interface engineering.

Experimental Methods

Sample Preparation and Device Fabrication

Black phosphorus flake with a thickness of ~15 nm was micromechanically exfoliated onto p-type silicon substrate with an ultra-thin HfO2 high-k gate dielectric of ~3.4 nm. The HfO2 was deposited by atomic layer deposition (ALD) process. Utilizing tetrakisethylmethylamino hafnium (TEMAH) and water precursors at a deposition temperature of 250 °C, a deposition rate of ~1 Å/cycle is achieved. For every cycle of deposition, the TEMAH precursor and the water precursors are pulsed at 0.015 seconds and 0.01 seconds respectively, followed by a waiting time of 10 seconds. During the deposition, nitrogen with a flow rate of 20 sccm is utilised as the carrier gas. This was followed by a sequential cleaning in acetone followed by isopropyl alcohol before the deposition of metal electrodes using nickel (Ni) through a combination of electron beam lithography (JEOL, JBX-6300FS) and electron-beam evaporation (Oerlikon, Univex 450B). The remaining photoresist was then lifted-off to complete the device fabrication. A 30 nm silicon-dioxide passivation layer was then deposited at room temperature using electron-beam evaporation (Oerlikon, Univex 450B) over the entire BP transistor to protect the device from photo-oxidation in ambient condition23. Subsequently, the devices were subjected to interface thermal treatment. The anneal conditions were varied from zero to 200 °C for one minute in nitrogen (N2) ambient to investigate the impact of thermal treatment on the structural and electrical properties of the BP transistors. Confocal Raman spectroscopy (WITec, Alpha300R) was utilized to analyze the influence of interface anneal temperature on the Raman shifts corresponding to the out-of-plane (A1g) and in-plane (B2g, A2g) phonon modes36.

Additional Information

How to cite this article: Ling, Z.-P. et al. Interface Engineering for the Enhancement of Carrier Transport in Black Phosphorus Transistor with Ultra-Thin High-k Gate Dielectric. Sci. Rep. 6, 26609; doi: 10.1038/srep26609 (2016).