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The era of hyper-scaling in electronics

Nature Electronics volume 1, pages 442–450 (2018)Cite this article

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An Author Correction to this article was published on 22 August 2018

This article has been updated

Abstract

In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometres, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. Here we argue that electronics is poised to enter a new, third era of scaling — hyper-scaling — in which resources are added when needed to meet the demands of data abundant workloads. This era will be driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques.

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Fig. 1: Three eras of CMOS technology scaling.
Fig. 2: Beyond-Boltzmann transistor concepts.
Fig. 3: Embedded volatile and non-volatile memory.
Fig. 4: Back-end-of-line transistor options.
Fig. 5: Near-monolithic performance with true heterogeneity.

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Change history

  • 22 August 2018

    In the version of this Perspective originally published, in the key for Fig. 2d the labels for the light-blue and dark-blue lines were mistakenly swapped. The light-blue line should have been labelled ‘Tunnel FET’ and the dark-blue line should have been labelled ‘Negative capacitance FET’. This has now been corrected.

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Acknowledgements

S.S., K.N. and S.D. acknowledge funding from ASCENT, one of six centres in JUMP (Joint University Microelectronics Program), a Semiconductor Research Corporation (S.R.C.) program sponsored by DARPA.

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Authors and Affiliations

  1. University of California, Berkeley, CA, USA

    Sayeef Salahuddin

  2. University of Notre Dame, Notre Dame, IN, USA

    Kai Ni & Suman Datta

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  1. Sayeef Salahuddin
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Contributions

S.S. and S.D. conceived the project, carried out the discussions and wrote the manuscripts. K.N. prepared the figures and co-wrote the section on memory benchmarking.

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Correspondence to Sayeef Salahuddin or Suman Datta.

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Salahuddin, S., Ni, K. & Datta, S. The era of hyper-scaling in electronics. Nat Electron 1, 442–450 (2018). https://doi.org/10.1038/s41928-018-0117-x

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