Towards epitaxial graphene p-n junctions as electrically programmable quantum resistance standards

Abstract

We report the fabrication and measurement of top gated epitaxial graphene p-n junctions where exfoliated hexagonal boron nitride (h-BN) is used as the gate dielectric. The four-terminal longitudinal resistance across a single junction is well quantized at the von Klitzing constant ${{\boldsymbol{R}}}_{{\boldsymbol{K}}}$ with a relative uncertainty of 10⁻⁷. After the exploration of numerous parameter spaces, we summarize the conditions upon which these devices could function as potential resistance standards. Furthermore, we offer designs of programmable electrical resistance standards over six orders of magnitude by using external gating.

Introduction

The advantageous electrical and optical properties of graphene have been well-studied^1,2,3,4. When compared to semiconductor heterostructures, epitaxial graphene (EG) on silicon carbide (SiC) has been identified as an ideal platform for resistance standards due to the observation of the quantum Hall effect (QHE) with resistance plateaus that span over a wide range of magnetic flux densities, large breakdown currents, and operation at relatively high temperatures^{5,6,7,8,9,10,11,12,13}. These resistance standards exclusively operate at the filling factor ν = 2, corresponding to the resistance value: $\frac{1}{2}\frac{h}{{e}^{2}}=\frac{1}{2}{R}_{K}$ [see additional information], where h is Planck’s constant and e is the elementary charge. Moreover, the realization of other values based on fundamental constants is a crucial milestone in resistance metrology that is still being explored with EG¹⁴. One approach is to connect multiple Hall bars in complicated parallel and series networks to create resistance values of $q{R}_{K}$ where q is a positive rational number^14,15,16. The other approach is to utilize the unique properties of graphene to build p-n junctions working in the quantum Hall regime that allow convenient resistance scaling¹⁷.

Due to its linear dispersion relation, where the characteristic Dirac point represents charge neutrality, it is easy to electronically dope graphene into bipolar carrier concentration regions, denoted as p (holes) or n (electrons), with external gates. Furthermore, the physics of graphene p-n junctions (pnJs) enables one to fabricate devices to access quantized resistance values that are multiples or fractions of $\frac{1}{2}{R}_{K}$¹⁷. When all of the regions of a device are in the quantum Hall regime but have different carrier concentrations and polarities, the measured longitudinal resistivities across one or several sets of pnJs depend on how the Landauer-Büttiker edge states equilibrate at the junction^18,19,20. There have been several reports about this behavior while using tunable gates to adjust the pnJ^{18,21,22,23,24}.

Graphene pnJ can be utilized to circumvent frequent technical difficulties resulting from the general use of metallic contacts and multiple device interconnections. In this work, we demonstrate highly accurate resistance quantization at ${R}_{K}$ in an EG pnJ device, measured with a direct current comparator (DCC) resistance bridge. The characterization measurements are summarized here, starting with a description of the device engineering. Comprehensive exploration of experimental parameter spaces (B field, gate voltages, temperature) was performed, enabling us to fully understand this EG pnJ, and further motivating us to discuss the conceptual realization of constructing a programmable quantized Hall resistance (PQHR) system.

Results

The EG Hall bar is shown in Fig. 1(a) indicated by the red dashed line with a width of 50 μm and the blue dashed line showing the perimeter of the h-BN flake, measured to have a thickness of 45 nm (d_BN). The atomic force microscope (AFM) image in Fig. 1(b) is a magnification of one of the top gate junctions, represented by the small black square in (a), with dashed gray lines used to help identify that region. The width of the gap between the two gates is approximately 150 nm, which is small enough to create a single pnJ. A cross-section illustration of the device is shown in Fig. 1(c) depicting the use of h-BN as a dielectric layer. The top gate quality was assessed by measuring the leakage current between top gate and EG. When a DC voltage was applied between graphene and the top gates G1 and G2 through the range of −15 V to 15 V, a leakage current of less than 1 nA was observed. For voltages that exceeded 15 V in either polarity, the leakage current rapidly increased beyond 1 nA, thus defining an upper and lower bound to the gate voltage magnitude. Due to excessive leakage currents, gate G3 in Fig. 1(a) was not used.

Figure 1

EG device description. (a) The optical image of the device shows the graphene Hall bar outlined by a red dashed line and the encapsulating h-BN layer enclosed by a blue dotted line. The width of the Hall bar channel is marked with a white arrow. Each used device contact is given a numerical designation and the top gates are labelled as G1, G2 and G3 and represented as digitally artificial colors of yellow, orange, and bronze, respectively. The upper (UE) and lower edges (LE) are marked with dashed white lines. The direction of the positive magnetic field for the measurements is out of the page. (b) The atomic force microscope image of the pnJ shows the magnified region enclosed by the black square in (a). (c) An illustration device’s cross section is provided.

One would ideally like to know the range of carrier densities attainable with these gates, and so we first focus on determining the carrier density parameter space in the unipolar case. The well-documented electrical and optical properties of the interfacial buffer layer as well as its interactions with EG allow one to expect inherent n-type doping^25,26,27. We employ a basic capacitance model to gain an insight into the expected doping. Let ${n}_{G}$ and ${E}_{F}$ be the electron density and Fermi level of the EG layer, respectively. The relationship between those two parameters and the gate voltage V_G is:^28,29

$$\frac{{C}_{ox}}{e}({V}_{G}-{V}_{D})=\frac{{C}_{\gamma 2}}{{C}_{s2}}[{n}_{G}+({C}_{s1}+{C}_{s2})\frac{{E}_{F}}{{e}^{2}}]$$

(1)

In equation (1), V_D is the voltage corresponding to the Dirac point, ${C}_{ox}=\frac{{{\epsilon }}_{BN}{{\epsilon }}_{0}}{{d}_{BN}}$ is the gate geometric capacitance (per unit area), with ${{\epsilon }}_{BN}$ and ${d}_{BN}$ as the dielectric constant and thickness of h-BN, respectively. The other constants are determined by the quantum capacitance of the charge transfer layers including EG, the buffer layer beneath, and the residual chemical doping between graphene and h-BN. Additionally, C_s is the additive capacitance of the quantum capacitance and the single layer gap of 0.3 nm between graphene and the adjacent layer.

The capacitance relations are listed here, with d = 0.3 nm as the distance between the EG and its adjacent neighboring layers, where the buffer is labelled by subscript $i=1$ and residual chemical doping is labelled by subscript $i=2$ such that: (1) quantum capacitance ${C}_{\gamma i}={\gamma }_{i}{e}^{2}$ (2) geometrical capacitance ${C}_{ci}=\frac{{{\epsilon }}_{i}}{d}$ and total capacitance (3) ${C}_{si}={(\frac{1}{{C}_{ci}}+\frac{1}{{C}_{\gamma i}})}^{-1}$. The used dielectric constants are ${{\epsilon }}_{BN}=3.9{{\epsilon }}_{0}$, ${{\epsilon }}_{1}=9.7{{\epsilon }}_{0}$, and ${{\epsilon }}_{2}=3{{\epsilon }}_{0}$, where ${{\epsilon }}_{0}$ is the vacuum permittivity^28,29. In the case of zero magnetic field, the relation between ${n}_{G}$ and ${E}_{F}$ is ${E}_{F}={\rm{\hbar }}{{\rm{\nu }}}_{F}\sqrt{\pi |{n}_{G}|}sign({n}_{G})$, while in nonzero magnetic field B, the total density can be found with ${n}_{G}={\int }_{0}^{{E}_{F}}D(E)dE$, with the density of states³⁰:

$$D(E)=\frac{{g}_{s}{g}_{\nu }eB}{h}{{\rm{\Sigma }}}_{N}\frac{1}{\sqrt{2\pi {s}^{2}}}exp[\frac{-{(E-{E}_{N})}^{2}}{2{s}^{2}}]$$

(2)

where ${E}_{N}={\nu }_{F}\sqrt{2|N|}sign(N)$ is the Landau level N, s = 12 meV, ${g}_{s}{g}_{\nu }=2$ are the spin and valley degeneracies.

Equation (2) gives the total density of states (DOS), which, when combined with equation (1), allows us to determine how ${n}_{G}$ varies as a function of unipolar gate voltage. This calculation also depends on the capacitance parameters ${\gamma }_{1}$ and ${\gamma }_{2}$, representing the two interfaces adjacent to the graphene sheet. In the case where ${\gamma }_{1}$ and ${\gamma }_{2}$ are zero, one assumes a freestanding EG layer with no charge transfer between interfaces. As the two parameters are modulated, one can fit this model to experimental data. Figure 2(a) shows measurements for R_xx and R_xy, collected at B = 0.2 T. Those two quantities are then converted into ${n}_{G}$ and $\mu$, as seen in Fig. 2(b) as orange data points and a green curve, respectively. The following formulas were used to calculate ${n}_{G}$ and the mobility: ${n}_{G}=\frac{1}{e(\frac{d{R}_{xy}}{dB})}$ and $\mu =\frac{1}{e{n}_{G}{R}_{xx}\frac{W}{L}}$. The capacitance model is plotted here as well, showing the case where EG is freestanding and the case where the model fits the data for ${n}_{G}$, which corresponds to ${\gamma }_{1}=1.2\times {10}^{14}e{V}^{-1}c{m}^{-2}$ and ${\gamma }_{2}=1.5\times {10}^{4}e{V}^{-1}c{m}^{-2}$. Note that there are four different ways to calculate ${n}_{G}$ and mobility using the data in Fig. 2(a). The results presented by the dashed lines in Fig. 2(b) are the mean of the calculations.

Figure 2

EG device characterization. (a) At B = 0.2 T and T = 1.7 K, the device’s longitudinal resistances (R_xx) in red and Hall resistances (R_xy) in blue are measured with respect to unipolar gate voltage. R_xx is measured for the upper and lower edge (UE and LE), shown as points and triangles, respectively, whereas the point and triangle symbols for R_xy represent just two different regions of the device. All legend numbers correspond to contact numbers from Fig. 1 (b) The carrier densities are measured (orange curves, dashed and dotted for the two different regions), the mobilities are calculated (green curve, with dashed and dotted appearances corresponding to the same two regions), and the capacitance models for both freestanding EG and EG undergoing charge transfer (due to adjacent neighboring layers) are plotted (pink dotted and dashed purple curves, respectively). The carrier densities and capacitance models are plotted on the left vertical axis, whereas the mobilities are plotted on the right vertical axis.

With the unipolar bounds of ${n}_{G}$ known as about 6 × 10¹¹ cm⁻² at a gate voltage of 15 V, V_G and B were used as independent variables to determine the boundary beyond which full quantization occurs. These measurements, accompanied by Hall resistance measurements, are shown in Fig. 3. In Fig. 3(a), the dashed lines are calculated from Equations (1) and (2) using the fitted results of to ${\gamma }_{1}$ and ${\gamma }_{2}$. From these measurements, one observes only two definitive regions of zero longitudinal resistance, which indicates that only the ν =± 2 plateau is accurately quantized.

Figure 3

Conditions for full quantization. (a) At T = 1.7 K, R_xx for the upper edge is measured as a function of unipolar gate voltage and magnetic field. Contact numbers correspond to those in Fig. 1. A model for determining the boundaries for quantization are marked in dotted cyan. R_xx clearly drops to zero past this boundary into the black-colored region. (b) R_xy measured in the G1 region is provided to verify that only ν =  ± 2 is well-quantized, with the same parabolic boundary appearing in the data.

After determining the magnetic field conditions for full quantization, we explore R_xx as a function of the two gate voltages in Fig. 4 at B = 14 T. The upper edge in Fig. 4(a) has zero resistance for three out of four quadrants in this parameter space. For the final quadrant, corresponding to G2 and G1 as an n-type and p-type region, respectively, R_xx takes on the quantized value of ${R}_{K}$ [see additional information]. Full quantization is further verified by the accompanying Hall resistance measurements for G2 and G1 seen in Fig. 4(b,d). The lower edge in Fig. 4(c) exhibits the same behavior when the gate polarities are reversed. Furthermore, the data is symmetric about the diagonal cut which intersects the Dirac points of G1 and G2. More information about the two Dirac point measurements can be seen in the Supplementary information.

Figure 4

R_xx and R_xy as a function of two gate voltages. (a) At B = 14 T (as shown in Fig. 1 (a)) and T = 1.7 K, R_xx for upper edge is measured as a function of two gate voltages. In both unipolar and one bipolar region, R_xx is measured across a low dissipation region, and thus takes on the expected value of zero. When the graphene under G2 and G1 is n-type and p-type, respectively, R_xx takes on the quantized value of ${R}_{K}$. (b) The corresponding Hall resistances for the same parameter space are shown to verify that the device is quantized. (c) The lower edge is measured as a function of two gate voltages and expectedly exhibits the same behavior when the polarity of the top gates is reversed. (d) With the Hall resistances verifying the quantization in the lower edge case, it becomes clear that all four maps are symmetric about a diagonal line which intersects the Dirac points of both G1 and G2.

One advantage of these observations of the longitudinal resistance taking on different values is that such values could potentially be used for electrically programmable quantum resistance standards. These observations motivated the continued exploration of how the longitudinal resistance of the pnJs can be accurately quantized at ${R}_{K}$ under appropriate gate conditions. In order to characterize the device for metrological purposes, critical currents of QHE breakdown must be known. Higher critical currents are generally beneficial for resistance metrology since they can both provide a better signal-to-noise ratio and an increased compatibility with commercial metrology equipment such as the DCC, voltage calibrators, and precision digital multimeters^31,32,33.

To measure the critical currents of the entire device as a function of two gate voltages, different circuits required assembly depending on which of the two quantized values of R_xx was being measured. Here, the critical current is defined as the point when is less than the relative uncertainty, indicating that the device is no longer exhibiting the QHE with full quantization. This condition will be further clarified later in the text. Figure 5(a) contains an illustration of the circuit used to measure the critical currents for the device while it is quantized. An example measurement representing how three out of four regions in the dual gate parameter space behave is shown in Fig. 5(b). In this example case, using ${V}_{G1}={V}_{G2}=7\,V$, the negative and positive critical current limits are found to be about −21 μA and 24 μA. The measured result can be well-described by the formula of variable range hopping (VRH) transport³⁴:

$${V}_{UE}\propto {I}_{DC}exp[-\sqrt{{I}_{0}/|{I}_{DC}|}].$$

Figure 5

Measurement techniques for finding the critical currents at different quantized values of R_xx. (a) A circuit diagram is illustrated for the experimental setup which allows one to determine the critical current bounds of the pnJ while R_xx is characterized by a region of low dissipation (i.e. a region yielding 0 Ω). (b) An example measurement for the circuit diagram in (a) shows that for a quantized device, zero voltage across the multimeter is expected for small applied currents, and once quantization breaks down, the device contributes a nonzero voltage drop to the measurement. The data points and data fitting curve are shown as black ‘X’ marks and a dashed red curve, respectively. (c) For the case when R_xx is quantized at ${R}_{K}$, a more intricate experimental setup is required involving the use of a standard resistor in series with the EG pnJ device to remove the large DC component for the differential measurement. (d) The circuit in (c) is a direct determination of the resistance, as defined by measuring differential voltage with respect to differential current. ${R}_{K}$ is automatically subtracted from the differential resistance to give a region where the subtraction yields zero. The data points and data fitting curve are shown as black triangles and a dashed red curve, respectively. For (b) and (d), the shaded green area marks a boundary, within which the applied current is still below the critical current.

For the case of ${R}_{xx}={R}_{K}$, a different circuit is required to measure the critical currents, shown in Fig. 5(c). The circuit essentially allows one to measure the differential resistance at different DC current biases. The measured differential resistance shown in Fig. 5(d) is approximately zero for the region between −23 μA and 21 μA, and can be fit with the formula:

$${R}_{diff}-{R}_{K}\propto [1+\frac{3}{2}\sqrt{{I}_{0}/|{I}_{DC}|}]{I}_{DC}\exp [-\sqrt{{I}_{0}/|{I}_{DC}|}].$$

As with Fig. 5(b), these regions below the critical currents are shaded in green.

The critical currents were then determined as a function of two gate voltages in Fig. 6. Visually, one can associate the intensity of a point in these dual gate parameter spaces with the endpoints of the green shaded area in Fig. 5(b,d). For instance, the black region in Fig. 6(a) corresponds to a value of 0 μA, meaning that the device is not accurately quantized. For the UE, if ${V}_{G1}={V}_{G2}=10V$ (see Fig. 6(a,b)), the ${I}_{c}^{-}$ and ${I}_{c}^{+}$ limits are about −60 μA and 40 μA, respectively.

Figure 6

Critical currents at different gate voltages. (a) At B = 14 T and T = 1.7 K, the negative limit of critical current ${I}_{c}^{-}$ is determined for the upper edge (UE). The scale is logarithmic in current and represents the data for three quadrants measured with the circuit in Fig. 5 (a) whereas the fourth quadrant (upper left corner) shows data measured with the circuit in Fig. 5 (c). The dotted white lines are a guide to visualize the Dirac points of regions G1 and G2. (b) The same type of data as (a) are shown, only representing the positive limit of critical current ${I}_{c}^{+}$. (c) Data are shown with the same conditions as (a), but with the measurement focusing on the LE of the device. (d) ${I}_{c}^{+}$ is determined for the lower edge (LE) in the same fashion as (b), with the main difference being the replacement of the logarithmic scale with a linear one to demonstrate the order-of-magnitude difference in critical current limits for certain unipolar or bipolar configurations.

Figure 6 gives a full understanding of the critical current limits ${I}_{c}^{-}$ and ${I}_{c}^{+}$ for the upper edge ((a) and (b)) and the lower edge ((c) and (d)) of the device. It should be noted that for the upper left corner of the maps in (a) and lower right in (b), the measurements were taken using the circuit shown in Fig. 5(c), and the other three quadrants, with respect to the Dirac points, were measured using the circuit in Fig. 5(a).

With the critical currents’ behavior generally understood for the two gate voltages, one final parameter was tested. For ${V}_{G1}=10V$ and ${V}_{G2}=-\,10V$, we monitored the lower edge for deviations from the quantized value of ${R}_{K}$ and ${I}_{c}^{-}$ and ${I}_{c}^{+}$ were determined as a function of temperature. The overall dependence of the deviations from ${R}_{K}$ as a function of current and temperature is presented in Fig. 7(a), and the dependence of the extracted critical currents ${I}_{c}^{-}$ and ${I}_{c}^{+}$ on temperature, for both polarities, are shown in Fig. 7(b).

Figure 7

Quantization as a function of temperature and critical current. (a) The deviation of R_xx from ${R}_{K}$, while the lower edge (LE) was quantized at ${R}_{K}$, was measured as a function of temperature and applied current. There is a clear boundary for the combination of current and temperature which permits full quantization at ${R}_{K}$. (b) The critical currents are plotted as a function of temperature for both polarities.

To assess the metrological usefulness of the pnJ device, the quantity ${R}_{xx,\le -{R}_{K}}$ was measured as a function of current used on the DCC (I_DC). The DCC, unlike its cryogenic counterparts, can provide turn-key resistance traceability for the most demanding applications, offering broader accessibility to these types of experiments³⁵. This measurement places the device in a four-terminal bridge configuration against a 10 kΩ standard resistor, traceable to ${R}_{K}$, with the results shown in Fig. 8(a). The measurement time for each data point with the DCC is 15 min, and the orange shaded region is magnified in Fig. 8(b) to clarify the deviation of the DCC measurements with respect to zero. The data are displayed as turquoise points whose standard deviations (1 s) are mostly smaller than the points. The right axis and its corresponding data, represented by black points, gives the relative uncertainty of each measurement as a function of I_DC. One important factor in resistance metrology is the level of precision one can achieve with such devices. In the case of this p-n junction, a precision of about 2 × 10⁷ was achieved. Recall that the breakdown current is determined when $\frac{|{\rm{\Delta }}{R}_{xx,LE}|}{{R}_{K}}$ is less than the relative uncertainty. The critical current for this case was 24 μA, and the region shaded in green encloses the current range one can potentially use for resistance metrology.

Figure 8

Accuracy of quantization. (a) The lower edge (LE) was compared against a 10 kΩ standard resistor with a DCC to give an accurate assessment of how well-quantized the device was when exhibiting a longitudinal resistance of ${R}_{K}$. The resistor was selected based on its traceability to a quantum resistance standard at the National Institute of Standards and Technology. The turquoise points show the DCC measurements as deviations from ${R}_{K}$ on the left axis and the relative uncertainties of those deviations with DC current. The relative uncertainties improve with increasing current, but the device loses its optimal quantization after the critical current of 24 μA. The shaded green area indicates the well-quantized region. (b) The beige shaded area in (a) is magnified to show the deviations’ error bars as well as the reference to zero deviation, marked as an orange dashed line. The error bars represent a 1σ deviation from the mean, where each data point represents an average of a set of data taken at each value of current.

Discussion

These data show that electrically programmable quantum resistance standards are feasible to build using pnJs as keystones. One can generalize these initial efforts for the future by proposing a specialized PQHR device, which will be described in more detail after explaining its most basic component, shown in Fig. 9(a). Consider p-type graphene formed into a device with N regions with the following conditions: (1) Region 1 contains a single gate controlled by a single input voltage. (2) Region 2 contains two gates controlled by another single voltage input. (3) Region 3 contains four gates controlled by a third single voltage input. (4) If the device is extended to N^th region, Region N contains ${2}^{N-1}$ gates controlled by a single voltage input. We call a device with a total of N regions an N-bit device, which can have a maximum of $2\ast ({2}^{N}-1)$ total pnJs. At each of the two ends of the graphene device, the usage of triple-series connection techniques is recommended to reduce the effect of contact and other resistances³¹.

Figure 9

Proposal of PQHR device for scalable and programmable standards. (a) An N-bit device is illustrated showing how each region is defined and the maximum number of pnJs that can be used. (b) This device, when connected in parallel with K copies of itself, becomes the foundation of the $(N,K)$ module. Each region has a set of gates that extend to all K parallel branches. (c) The proposed device is illustrated and composed of eight $(N,K)$ modules, four of which are in parallel in stage 1, three of which are parallel in stage 2, and a lone module in stage 3. All three stages are connected in series and all connections and contacts are proposed to be superconducting metal to eliminate the contact resistance to the greatest possible extent. The modules in stage 1 are 8-bit devices with more than 100 parallel copies per module, whereas the modules in stage 2 are 3-bit devices with four or fewer parallel copies per module. Stage 3 is a single 12-bit device with no additional parallel branches. These numbers for $(N,K)$ are required should one wish to reproduce the values in Table 1.

For example, in the eventual proposed device, the largest device contains 8 regions (and is an 8-bit device), where Region 8 contains 128 gates, all controlled by a single voltage input. In this case, there are 8 unique voltage sources for the 8 regions. All gates, when controlled by the voltage source, can be activated to shift the graphene carrier density to n-type, creating many pnJs. Let us denote when a region has its gates activated by defining the gate control parameter ${b}_{i}=1\vee 0$. If Region 3 has its gates activated, then ${b}_{3}=1$. We use this notation to count the total number of active pnJs in the given device: ${b}_{N}{2}^{N-1}+{b}_{N-1}{2}^{N-2}+{b}_{N-2}{2}^{N-3}+\cdots +{b}_{1}{2}^{0}$. Notice that when all N regions are activated, the total number above is a geometric sum for the maximum we noted in the previous paragraph ($2\ast ({2}^{N}-1)$). Furthermore, we use the gate control parameter to form a binary string representing a device which has some (or all) of its N regions activated: ${b}_{N}{b}_{N-1}{b}_{N-2}\,\cdots \,{b}_{1}$. In the 8-bit device case, if all eight regions are activated, then the string is simply: $11111111$. If only regions 1, 3, 5, and 7 are activated, then the string is: $01010101$.

We now describe the second major component of this proposed device, shown in Fig. 9(b). An N-bit device can be used as one of many parallel devices, where K indicates the number of parallel N-bit devices. The important thing to note here is that all K devices share the gate control parameter, and thus the binary string is identical for all devices in parallel. If we have ten 8-bit devices in parallel, then activating Region 3 would mean doing so for all ten devices, as the gates stretch over all devices. This is illustrated in Fig. 9(b) as two n-type regions being identically activated over several devices by two long gates. This configuration allows an equal amount of current to flow in each of the K branches and can be condensed by using two numbers to describe it: N, for the number of bits per isolated device, and K, the number of isolated devices in parallel. Let’s now call this entire configuration an $(N,K)$ module.

The proposed specialized device for achieving seven decades of resistance is illustrated in Fig. 9(c). There are three stages of modules between the source and drain. Stage 1 contains four $(N,K)$ modules connected in parallel, stage 2 contains three $(N,K)$ modules in parallel, and stage 3 contains just one $(N,K)$ module. All three stages are connected in series with superconducting metal contacts.

When the numbers N and K, along with the gate control parameter binary strings, are carefully selected, a wide range of resistance decades can be achieved. For example, Table 1 shows seven decades and their corresponding parameters. The example parameters are selected to ensure low deviation (<1 µΩ/Ω) from decade values. The current flow is from source to drain and voltages can be measured using any two voltage probes shown in Fig. 9(c), labelled A, B, C and D.

Table 1 Possible resistance decades achievable with programmable standards.

The proposed PQHR device in Fig. 9(c) requires a total number of 53 voltage inputs to control 53 distinct regions (32 total regions in stage 1, 9 total regions in stage 2, and 12 total regions in stage 3). When fabricating such a device, the graphene widths will be identical within each stage, but will scale from stage to stage with the ratio of 1:7:3654, where graphene in first stage would be the narrowest. This would require, with a narrowest channel of 10 µm in stage 1 components, a stage 3 component width of about 3.7 cm.

Comprehensive assessments of the magnetic field, carrier density, top gate voltage, critical current, temperature, and accurate quantization parameter spaces were conducted to determine the conditions required for an EG pnJ device to be metrologically useful. In conclusion, after fabricating and measuring an EG pnJ using h-BN as the gate dielectric, we demonstrated that accurate quantization of zero and ${R}_{K}$ can be exhibited by the device’s longitudinal resistance with a relative uncertainty on the order of 10⁻⁷ as measured by a DCC resistance bridge. This work begins a new avenue in the production of quantum resistance standards and enables their accurate scaling for future metrology applications.

Methods

Sample growth

The methods for growing high quality epitaxial graphene are well-reported^5,6,11,36. EG is formed by sublimating Si atoms from the silicon face of SiC as part of an annealing process. Samples were grown on square SiC chips diced from on-axis 4H-SiC(0001) semi-insulating wafers (CREE) [see additional information]. SiC chips were submerged in a 5:1 diluted solution of hydrofluoric acid and deionized water prior to the growth process. Chips were rinsed with deionized water and placed on a polished pyrolytic graphite substrate (SPI Glas 22) [see additional information]. Chips were processed with AZ5214E to utilize polymer-assisted sublimation growth techniques³⁶. The silicon face was resting against the graphite in order for the gap between the two surfaces to create a diffusion barrier for escaping Si atoms. This configuration promotes homogeneous graphene growth conditions¹¹. The annealing process was performed with a graphite-lined resistive-element furnace (Materials Research Furnaces Inc.) [see additional information], with heating and cooling rates of about 1.5 °C/s. The growth stage was performed in an ambient argon environment at 1900 °C⁵.

Sample fabrication

The grown EG was evaluated with confocal laser scanning and optical microscopy as an efficient way to identify large areas of successful growth³⁷. Using photolithography, both the Hall bar geometry and the contact pads are fabricated in steps that are presented in detail in other works^5,38. In summary, protective layers of Pd and Au are deposited on the EG to prevent organic contamination. While protected, the EG is etched into the desired device shape, with the final step being the removal of the protective layers from the Hall bar using a solution of 1:1 aqua regia to deionized water. To fabricate top gates, hexagonal boron nitride (h-BN) flakes are exfoliated onto polydimethylsiloxane (PDMS) and their quality and size are inspected with a dark field optical microscope and AFM. The PDMS slab carrying the selected h-BN flake is then mounted on a glass slide arm for positioning and alignment with the EG device, accurate to within a few μm, using a homemade transfer stage. The h-BN flake is slowly lowered towards the EG surface until contact is made. The stage, upon which the EG device rests, is then heated to 110 °C to dislodge the h-BN flake from the PDMS substrate. A standard electron beam lithography process is used to fabricate metal. All contacts had resistances of approximately 100 Ω in the QHE regime.