Shen et al. reply

We recently demonstrated an ultracompact integrated polarization beamsplitter (PBS) utilizing nanophotonic dielectric structures1. Sigmund et al. raised concerns regarding our paper2. Our response is as follows.

First, Sigmund et al. point out the ambiguousness of defining performance metrics for such devices, while reducing their footprint. It is well known that the performance of many integrated photonic devices is intimately linked to their size. The approach we followed was to design devices whose performance is on par with conventional devices, but with a greatly reduced footprint. For example, in our paper, the PBS has a designed average transmission efficiency of ∼75% over an operating bandwidth of 80 nm, which is comparable to that of conventional integrated photonic PBS devices that are ∼19 times larger3.

Second, Sigmund et al. cast doubt on the claim that our PBS is the smallest ever demonstrated by citing Guan and colleagues' simulations of a plasmonic PBS4. However, Guan et al. did not experimentally demonstrate their device as we carefully pointed out in our paper. Therefore, we reiterate our claim that our PBS is the smallest such device (experimentally) demonstrated to date.

Third, we acknowledge the pioneering work of Sigmund et al. and apologize for the honest mistake of missing this work.

Fourth, Sigmund et al. point out that in-plane geometric variations of a device are more important than device thickness. We did analyse the impact of in-plane geometric errors on device performance, which is included in the Supplementary Information associated with our paper. We emphasized the impact of device thickness in the main text for two reasons. First, we treated this as an optimization variable to improve the device performance, and custom-made the requisite silicon-on-insulator substrates. The device thickness varies due to our process limitations. Second, the technique used to etch our devices (focused-ion-beam lithography) is not very selective to silicon compared with silicon dioxide, which means that the top silicon layer can be over-etched and the oxide layer beneath is unintentionally affected. Therefore, we need to account for possible discrepancies between the device (silicon) thickness before and after etching.

Sigmund et al. are worried that our computation time would increase significantly with the increase in our design variables. We acknowledge that our approach is computationally intensive, but also point out that unlike the previous approaches, we are able to design devices with performance that is comparable to much larger conventional devices. Most importantly, our design algorithm is parallelizable and using larger clusters of processors will significantly decrease the computation time.

Finally, Sigmund et al. claim that we speculated about the use of our technique in a variety of applications. We point out that this is not speculation, as we have demonstrated many of these devices, including free-space metamaterial polarizers5, free-space metamaterial diodes6, integrated metamaterial diodes7, integrated free-space-to-waveguide couplers8, and a variety of designs for enhancing light-trapping in thin-film photovoltaics9,10,11,12,13. We agree with Sigmund et al. that topology optimization has developed over two decades. However, its application to enhancing photonic functionality (for example, by combining mode conversion and polarization splitting into a single device), while decreasing the footprint of integrated photonic devices as we show in our paper is unique.