Solar cells are attractive candidates for clean and renewable power1,2; with miniaturization, they might also serve as integrated power sources for nanoelectronic systems. The use of nanostructures or nanostructured materials represents a general approach to reduce both cost and size and to improve efficiency in photovoltaics1,2,3,4,5,6,7,8,9. Nanoparticles, nanorods and nanowires have been used to improve charge collection efficiency in polymer-blend4 and dye-sensitized solar cells5,6, to demonstrate carrier multiplication7, and to enable low-temperature processing of photovoltaic devices3,4,5,6. Moreover, recent theoretical studies have indicated that coaxial nanowire structures could improve carrier collection and overall efficiency with respect to single-crystal bulk semiconductors of the same materials8,9. However, solar cells based on hybrid nanoarchitectures suffer from relatively low efficiencies and poor stabilities1. In addition, previous studies have not yet addressed their use as photovoltaic power elements in nanoelectronics. Here we report the realization of p-type/intrinsic/n-type (p-i-n) coaxial silicon nanowire solar cells. Under one solar equivalent (1-sun) illumination, the p-i-n silicon nanowire elements yield a maximum power output of up to 200 pW per nanowire device and an apparent energy conversion efficiency of up to 3.4 per cent, with stable and improved efficiencies achievable at high-flux illuminations. Furthermore, we show that individual and interconnected silicon nanowire photovoltaic elements can serve as robust power sources to drive functional nanoelectronic sensors and logic gates. These coaxial silicon nanowire photovoltaic elements provide a new nanoscale test bed for studies of photoinduced energy/charge transport and artificial photosynthesis10, and might find general usage as elements for powering ultralow-power electronics11 and diverse nanosystems12,13.
We thank D. W. Pang, D. C. Bell, H. G. Park, H. S. Choe, H. Yan and P. Xie for help with experiment and data analysis. C.M.L. acknowledges support from the MITRE Corporation and the Air Force Office of Scientific Research, and T.J.K. acknowledges an NSF graduate fellowship.
Author Contributions C.M.L., B.T., X.Z. and T.J.K. designed the experiments. B.T., X.Z., T.J.K., Y.F., N.Y. and G.Y. performed experiments and analyses. C.M.L., B.T., X.Z. and T.J.K. wrote the paper. All authors discussed the results and commented on the manuscript.
This file contains Supplementary Figure S1, which shows periodically-etched p-i-n coaxial silicon nanowires and corresponding logic gates; and Supplementary Figure S2, which shows light/dark current-voltage curves for a p-i-n coaxial silicon nanowire before and after patterning an optical mask on the nanowire.